Why ML always use LEAVE but not ENTER?

[Mark Jones]

In every proc, the stack frame is created by PUSH EBP and MOV EBP,ESP instead of ENTER. Why is this?

Code:

myProc PROC USES ESI EDI
; nothing in here...
myProc ENDP

00405910  /.  55            PUSH EBP
00405911  |.  8BEC         MOV EBP,ESP
00405913  |.  56            PUSH ESI
00405914  |.  57            PUSH EDI                                ;  ntdll.7C910738
00405915  |.  5F            POP EDI                                  ;  kernel32.7C816D4F
00405916  |.  5E            POP ESI                                  ;  kernel32.7C816D4F
00405917  |.  C9            LEAVE
00405918  \.  C2 0800     RETN 8

[bushpilot]

Well, I can't answer ... but I do know that the AMD optimization manual recommends the use of leave, but does not recommend using enter.  I too have wondered why.

Greg

[arafel]

According to Agner`s optimization manual on P4 ENTER has latency of 25 and takes 4uops. While "push ebp with mov ebp, esp" in cumulative have latency of 1.5 and take 2uops. On PIII ENTER seems to be slower as well. Perhaps this is the reason why masm avoids enter by default.

[hutch--]

For whatever reason, ENTER has been slow for a long time where LEAVE still performs OK on most of the later machines. It is shorter but it has probably retained its performance because many C compilers have used the LEAVE exit from a stack frames as well.

[P1]

The uP is female.  You always enter slowly, leave as quickly as possible.   

Regards,  P1 

[no-one]

Hutch,
Go ahead and delete my posts but you cannot shut me up.  The above posing is appalling and you can not deny it.

Paul

[hutch--]

Paul,

As you know I am an Australian and I live in a culture that has considerably more robust humour than you have seen here in this topic. If I told you some of the jokes that can be told in polite company here, your hair would curl. Now I suggest that the argument you have in mind is not one that should be placed in a technical forum where a member has asked a question but back in the direction that it came from which is not here.

We are not internet policemen in this forum and never will be and when there are differences between people which is outside of this forum in its origin, it is simply not our task to interfere in that business. What I would suggest is that personal issue be left out of this forum and be dealt with elsewhere as they have no place here.

Now I will ask this much of you, please leave this matter alone in this forum as it is simply not our business and please use your normal name account.

[no-one]

For you, I will do this.  But I am still considering leaving.

My culture, from Massachusetts, is Puritanical and as Puritans we are ultra-conservative and such things are just not allowed in decent communications.  I will not change who I am and if I am subjected to things that I find offensive, I will react to them.  Trying to justify this type of actions will just fall on deaf ears in my case as I will not pollute my thought processes with such things.  I am aware of the history of Australians.

Paul

[savage]

So back to the topic...

Why did intel make it so friggin slow?

P.S.   Paul, I'm absolutely sure P1 means no harm by what he said.  And of course, he is definitely not serious, he's speaking with pure humor. I'm aware that many people are offended, but ALWAYS keep in mind that anything goes on the internet, so try not to take anything too personally.   

[hutch--]

Savage,

Its usually the case with processor design that if an instruction is redundant, it gets shoved into much slower micro-code so that the more speed critical stuff can occupy the higher speed areas of direct silicon. The preferred instructions like MOV, ADD SUB CMP etc .... get used far more often so they get priority in terms of being more directly constructed on the silicon chip wafer.

With ENTER, its probably because a PUSH and a MOV are easier to perform as two fast direct silicon opcodes than wasting the space on an older design instruction which cannot be used for another purpose.

There is another factor that processors use a lower level set of internals that the original 8088 instruction set and this leans towards far simpler instructions that complex ones. There are a few exceptions which are hard coded into some Intel processors and these are special case circuitry with REP MOVSD/LODSD and perhaps a couple of others. The instructions are so commonly used that they have special case circuits in the processors to keep their speed up to other instructions.

In the case of LEAVE, it is probably becuase many C compiler as well as MASM use LEAVE that it still performs reasonably well.

[savage]

I know this sounds like a naive question, but can't they just make the processor interpret ENTER and translate it internally as the better version? Or anything like that?

[Stan Hebben]

That's what happens, but the process of conversion slows down the processor. (all vectorpath instructions are translated in micro-ops)

[Ossa]

Basically the more commonly used instructions are the ones that are given the greatest speed to make code overall faster. If the enter instruction were made faster, some other instructions will end up slower which would slow other code down... it's an engineering trade-off and they decided (rightly I think) that enter could be made quite slow.

Ossa

[savage]

Ok, so....... if it's internally translated to the same thing, why is it slower overall from the stretched out version?

[Stan Hebben]

Assembly/Compiler Coding Rule 40. (ML impact, M generality)

Avoid using complex instructions (for example, enter, leave, or loop) that have more than four μops and require multiple cycles to decode.
Use sequences of simple instructions instead.

Complex instructions may save architectural registers, but incur a penalty of 4 μops to set up parameters for the microcode ROM.

The decoding takes some time. Using simple instructions instead of complex ones avoids the decoding, and is faster.

Stan